1. Field of the Invention
The present invention pertains to the field of computers. More particularly, this invention relates to cache memory systems used in computing systems.
2. Background
Computer technology is continuously advancing, resulting in microprocessors which operate at faster and faster speeds. In order to take full advantage of these higher-speed microprocessors, data storage capabilities must keep up with the increased speed. High-speed memory, however, is very expensive, with the cost being further amplified by the large amount of memory which many modern software programs require.
One solution to the problem of expensive memory is that of a cache memory subsystem. A cache memory subsystem is a memory unit which is generally much smaller than the system memory unit but which operates at a significantly higher speed than the system memory. The goal of the cache memory is to contain the information (whether it be data or instructions) that the microprocessor is going to use next. This information can then be returned to the microprocessor much more quickly, due to the higher speed of the cache memory.
The cache memory is typically much smaller than the system memory, thus, only a portion of the memory address is used to determine which location in the cache memory information should be placed in. This portion is referred to as the "index." A second portion of the memory address, generally referred to as the "tag portion," is then used to determine whether subsequent requests for information which match that particular location are for the data currently stored in that location. Therefore, multiple system memory addresses reference the same location in the cache memory.
The operation of cache memory subsystems varies, however, in general data is swapped between the system memory and the cache memory. When the microprocessor requests information from memory, for example, either an instruction it is going to execute or data related to an instruction, it sends the memory address of the desired information to the cache memory. If the cache memory contains the information, it issues a signal to the microprocessor indicating so; this signal is generally termed a "hit." The cache memory then returns the requested information to the microprocessor. Thus, the microprocessor receives the requested information more quickly due to the faster speed of the cache memory.
If, however, the cache memory does not contain the information requested by the microprocessor, then a signal, generally termed a "miss," is returned to the microprocessor. The miss indicates to the microprocessor that it must retrieve the information from the slower system memory. Alternatively, the cache memory controller may retrieve the information from the system memory, and return it to the microprocessor.
Regardless of whether the microprocessor or the cache controller retrieves the information from the system memory, the retrieved information is returned to the microprocessor and is also stored in the cache memory. When the microprocessor requests a memory address which corresponds to a location in the cache memory which is already used by another cache line, then a conflict occurs. In some systems, this situation is resolved by transferring the information stored in a particular location of the cache memory into system memory and transferring the information stored in system memory into that particular location of the cache memory.
Whether the cache memory must transfer the information to the system memory when a conflict occurs is also dependent on the cache policy employed. For example, some cache policies (generally referred to as "write-through" policies) transfer the information to the system memory whenever the information in the cache is updated. Thus, when retrieving new information from the system memory, information in the cache need not be transferred to the system memory. Other cache policies (generally referred to as "write-back" policies), however, transfer cache lines to the system memory only when a cache line conflict occurs and the cache line has been modified (generally referred to as being "dirty").
Regardless of whether the cache memory must transfer information in a particular location to the system memory in the event of a cache miss, information from the system memory is transferred to the cache memory. The retrieval of information from the system memory into the cache memory is typically referred to as "fetching" the information. This fetching of information from the system memory is a slow operation relative to the speed of the processor, due to the slower speed of the system memory as well as the speed of the system bus. Thus, this speed difference can result in situations where the processor issues additional requests to the cache memory while the cache memory is in the process of fetching information from the system memory.
When the cache memory is fetching information from the system memory, care must be taken to ensure that cache integrity is maintained. For example, if the processor issues a read request for memory address A which misses the cache memory, then the cache memory begins the process of fetching the information at address A from system memory. However, the processor may then issue a second request for memory address B before the cache memory has completed the fetch of address A from system memory. Care must then be taken to ensure that, if address A and address B map into the same set, the cache memory does not return the wrong information to the processor for either request.
One method of ensuring the correct information is returned to the processor is to "block" all requests from the processor while the cache memory is fetching information from the system memory. That is, no requests from the processor are serviced by the cache memory until the information being fetched is actually stored in the cache memory. This method, however, causes a delay for the processor while it waits to be "unblocked." Due to the speed difference between the system memory and the processor, this can be a substantial delay.
Thus, it would be beneficial to provide a method of efficiently using a cache memory system to support a microprocessor.
It would further be beneficial to provide a cache memory system which reduces blocking of requests from a processor, while at the same time ensures the correct information is returned to the processor.
The present invention provides for these and other advantageous results.